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74VHC393 Dual 4-Bit Binary Counter
March 1993 Revised February 2005
74VHC393 Dual 4-Bit Binary Counter
General Description
The VHC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It contains two independent counter circuits in one package, so that counting or frequency division of 8 binary bits can be achieved with one IC. This device changes state on the negative going transition of the CLOCK pulse. The counter can be reset to "0" (Q0-Q3 "L") by a HIGH at the CLEAR input regardless of other inputs. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: fMAX
170 MHz (typ) at TA VNIL
25qC 25qC
s Low power dissipation: ICC s High noise immunity: VNIH
4 PA (max) at TA
28% VCC (min)
s Power down protection is provided on all inputs s Pin and function compatible with 74HC393
Ordering Code:
Order Number 74VHC393M 74VHC393SJ 74VHC393MTC 74VHC393MTCX_NL (Note 1) 74VHC393N Package Number M14A M14D MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names CLR1, CLR2 CP1, CP2 QA, QB, QC, QD Description Clear Inputs Clock Pulse Inputs Outputs
(c) 2005 Fairchild Semiconductor Corporation
DS011571
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74VHC393
Truth Table
Inputs CP X CLR H L L
X: Don't Care
Outputs QA L QB L QC L QD L
Count Up No Change
System Diagram
Timing Chart
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74VHC393
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260qC
0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC
Recommended Operating Conditions (Note 3)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC VCC 3.3V r 0.3V 5.0V r 0.5V 0 a 100 ns/V 0 a 20 ns/V 2.0V to 5.5V 0V to 5.5V 0V to VCC
40qC to 85qC
Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 5.5 2.0 3.0 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 TA Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V IOL IOL VIN VIN 4 mA 8 mA V V VIN IOH IOH V IH IOL or VIL V 25qC Typ Max TA
40qC to 85qC
Max
Min 1.50 0.7 VCC
Units V
Conditions
0.50 0.3 VCC
V VIN V IH IOH or VIL
50 PA
4 mA 8 mA
50 PA
r0.1
4.0
r1.0
40.0
PA PA
5.5V or GND VCC or GND
3
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74VHC393
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time (CP -QA) tPLH tPHL Propagation Delay Time (CP -QB) tPLH tPHL Propagation Delay Time (CP -QC) tPLH tPHL Propagation Delay Time (CP -QD) tPLH tPHL Propagation Delay Time (CLR-Qn) fMAX Maximum Clock 5.0 r 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load Average operating current can be obtained by the equation: ICC(opr.) CPD*VCC*fIN ICC/2 (per Counter)
VCC (V) 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3
TA Min
25qC Typ 8.6 11.1 5.8 7.3 10.2 12.7 6.8 8.3 11.7 14.2 7.7 9.2 13.0 15.5 8.5 10.0 7.9 10.4 5.4 6.9 Max 13.2 16.7 8.5 10.5 15.8 19.3 9.8 11.8 18.0 21.5 11.2 13.2 19.7 23.2 12.5 14.5 12.3 15.8 8.1 10.1
TA
40qC to 85qC
Max 15.5 19.0 10.0 12.0 18.5 22.0 11.5 13.5 21.0 24.5 13.0 15.0 23.0 26.5 14.5 16.5 14.5 18.0 9.5 11.5
Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 65 35 105 75
Units ns ns ns ns ns ns ns ns ns ns
Conditions CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL VCC Open 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF
75 45 125 85
120 65 170 115 4 23 10
MHz
10
pF pF
(Note 4)
AC Operating Requirements
Symbol tW(L) tW(H) tW(H) tREM Parameter Minimum Pulse Width (CP) Minimum Pulse Width (CLR) Minimum Removal Time VCC (V) 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 TA Typ 25qC TA 5.0 5.0 5.0 5.0 5.0 4.0
40qC to 85qC
5.0 5.0 5.0 5.0 5.0 4.0
Guaranteed Minimum
Units ns ns ns
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74VHC393
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
5
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74VHC393
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74VHC393
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
7
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74VHC393 Dual 4-Bit Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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